From 26d94b940e1154ada068928666699deb15957c89 Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Sat, 21 Aug 2021 20:45:57 -0700 Subject: [PATCH] fusee-cpp: a little more init in SecureInitialize --- libexosphere/include/exosphere/clkrst.hpp | 1 + libexosphere/source/clkrst/clkrst_api.cpp | 8 ++++++++ libvapours/include/vapours/tegra/tegra_clkrst.hpp | 9 +++++++++ 3 files changed, 18 insertions(+) diff --git a/libexosphere/include/exosphere/clkrst.hpp b/libexosphere/include/exosphere/clkrst.hpp index 3299197a..95303bcb 100644 --- a/libexosphere/include/exosphere/clkrst.hpp +++ b/libexosphere/include/exosphere/clkrst.hpp @@ -29,6 +29,7 @@ namespace ams::clkrst { void EnableI2c1Clock(); void EnableI2c5Clock(); + void EnableSeClock(); void EnableCldvfsClock(); void EnableTzramClock(); diff --git a/libexosphere/source/clkrst/clkrst_api.cpp b/libexosphere/source/clkrst/clkrst_api.cpp index 3227a321..fe2aa455 100644 --- a/libexosphere/source/clkrst/clkrst_api.cpp +++ b/libexosphere/source/clkrst/clkrst_api.cpp @@ -82,6 +82,7 @@ namespace ams::clkrst { DEFINE_CLOCK_PARAMETERS(UartCClock, H, UARTC, PLLP_OUT0, 0); DEFINE_CLOCK_PARAMETERS(I2c1Clock, L, I2C1, CLK_M, 0); DEFINE_CLOCK_PARAMETERS(I2c5Clock, H, I2C5, CLK_M, 0); + DEFINE_CLOCK_PARAMETERS(SeClock, V, SE, PLLP_OUT0, 0); DEFINE_CLOCK_PARAMETERS(ActmonClock, V, ACTMON, CLK_M, 0); DEFINE_CLOCK_PARAMETERS(Host1xClock, L, HOST1X, PLLP_OUT0, 3); @@ -129,6 +130,13 @@ namespace ams::clkrst { EnableClock(I2c5Clock); } + void EnableSeClock() { + EnableClock(SeClock); + if (fuse::GetSocType() == fuse::SocType_Mariko) { + reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_CLK_SOURCE_SE, CLK_RST_REG_BITS_ENUM(CLK_SOURCE_SE_CLK_LOCK, ENABLE)); + } + } + void EnableCldvfsClock() { EnableClock(CldvfsClock); } diff --git a/libvapours/include/vapours/tegra/tegra_clkrst.hpp b/libvapours/include/vapours/tegra/tegra_clkrst.hpp index 738893bc..6d7fc51e 100644 --- a/libvapours/include/vapours/tegra/tegra_clkrst.hpp +++ b/libvapours/include/vapours/tegra/tegra_clkrst.hpp @@ -156,6 +156,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE); #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C) #define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X (0x180) #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 (0x198) +#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC (0x19C) #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0) #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 (0x1B8) #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 (0x1BC) @@ -165,6 +166,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE); #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 (0x3C4) #define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8) #define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 (0x410) +#define CLK_RST_CONTROLLER_CLK_SOURCE_SE (0x42C) #define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP (0x620) #define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF (0x62C) #define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC (0x630) @@ -245,6 +247,8 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE); #define CLK_RST_CONTROLLER_CLK_ENB_TZRAM_INDEX (0x1E) +#define CLK_RST_CONTROLLER_CLK_ENB_SE_INDEX (0x1F) + #define CLK_RST_CONTROLLER_CLK_ENB_HOST1X_INDEX (0x1C) #define CLK_RST_CONTROLLER_CLK_ENB_TSEC_INDEX (0x13) #define CLK_RST_CONTROLLER_CLK_ENB_SOR0_INDEX (0x16) @@ -298,10 +302,15 @@ DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_VI_VI_CLK_SRC, 29, RESERVED0, PLLC2 DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_HOST1X_HOST1X_CLK_SRC, 29, PLLC4_OUT1, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT2, PLLP_OUT0, CLK_M, PLLA_OUT0, PLLC4_OUT0); +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, 29, PLLM_OUT0, PLLC_OUT0, PLLP_OUT0, CLK_M, PLLM_UD, PLLMB_UD, PLLMB_OUT0, PLLP_UD); + DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_NVENC_NVENC_CLK_SRC, 29, RESERVED0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, PLLP_OUT0, RESERVED5, PLLA1_OUT0, CLK_M); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_TSEC_TSEC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, RESERVED4, PLLA1_OUT0, CLK_M, PLLC4_OUT0); +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SE_SE_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, RSVD4, PLLA1_OUT0, CLK_M, PLLC4_OUT0); +DEFINE_CLK_RST_REG_BIT_ENUM(CLK_SOURCE_SE_CLK_LOCK, 8, DISABLE, ENABLE); + DEFINE_CLK_RST_REG_BIT_ENUM(CLK_SOURCE_SOR1_SOR1_CLK_SEL0, 14, MUX, SOR1_BRICK_OUTPUT); DEFINE_CLK_RST_REG_BIT_ENUM(CLK_SOURCE_SOR1_SOR1_CLK_SEL1, 15, SAFE_CLOCK, SOR1_CLOCK_SWITCH);