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fusee_cpp: import full erista mtc logic

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This commit is contained in:
Michael Scire 2021-08-27 16:18:23 -07:00
parent 9ca9c59a19
commit 0d31962902
2 changed files with 13 additions and 0 deletions
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1
libvapours/include/vapours/tegra/tegra_clkrst.hpp
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@ -207,6 +207,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE);
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL (0x66C) #define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL (0x66C)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM (0x694) #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM (0x694)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC (0x6A4) #define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC (0x6A4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE (0x724)
/* RST_DEV_*_SET */ /* RST_DEV_*_SET */
#define CLK_RST_CONTROLLER_RST_DEV_L_SET (0x300) #define CLK_RST_CONTROLLER_RST_DEV_L_SET (0x300)

12
libvapours/include/vapours/tegra/tegra_emc.hpp
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@ -534,6 +534,16 @@
#define EMC_TRAINING_PATRAM_DQ (0xE64) #define EMC_TRAINING_PATRAM_DQ (0xE64)
#define EMC_TRAINING_PATRAM_DMI (0xE68) #define EMC_TRAINING_PATRAM_DMI (0xE68)
#define EMC_TRAINING_VREF_SETTLE (0xE6C) #define EMC_TRAINING_VREF_SETTLE (0xE6C)
#define EMC_TRAINING_RW_OFFSET_IB_BYTE0 (0xE98)
#define EMC_TRAINING_RW_OFFSET_IB_BYTE1 (0xE9C)
#define EMC_TRAINING_RW_OFFSET_IB_BYTE2 (0xEA0)
#define EMC_TRAINING_RW_OFFSET_IB_BYTE3 (0xEA4)
#define EMC_TRAINING_RW_OFFSET_IB_MISC (0xEA8)
#define EMC_TRAINING_RW_OFFSET_OB_BYTE0 (0xEAC)
#define EMC_TRAINING_RW_OFFSET_OB_BYTE1 (0xEB0)
#define EMC_TRAINING_RW_OFFSET_OB_BYTE2 (0xEB4)
#define EMC_TRAINING_RW_OFFSET_OB_BYTE3 (0xEB8)
#define EMC_TRAINING_RW_OFFSET_OB_MISC (0xEBC)
#define EMC_TRAINING_OPT_CA_VREF (0xEC0) #define EMC_TRAINING_OPT_CA_VREF (0xEC0)
#define EMC_TRAINING_OPT_DQ_OB_VREF (0xEC4) #define EMC_TRAINING_OPT_DQ_OB_VREF (0xEC4)
#define EMC_TRAINING_QUSE_VREF_CTRL (0xED0) #define EMC_TRAINING_QUSE_VREF_CTRL (0xED0)
@ -594,6 +604,7 @@ DEFINE_EMC_REG(ZCAL_INTERVAL_HI, 10, 14);
DEFINE_EMC_REG(PMC_SCRATCH3_DDR_CNTRL, 0, 19); DEFINE_EMC_REG(PMC_SCRATCH3_DDR_CNTRL, 0, 19);
DEFINE_EMC_REG_BIT_ENUM(PMC_SCRATCH3_WEAK_BIAS, 30, DISABLED, ENABLED); DEFINE_EMC_REG_BIT_ENUM(PMC_SCRATCH3_WEAK_BIAS, 30, DISABLED, ENABLED);
DEFINE_EMC_REG_BIT_ENUM(FBIO_CFG7_CH0_ENABLE, 1, DISABLE, ENABLE);
DEFINE_EMC_REG_BIT_ENUM(FBIO_CFG7_CH1_ENABLE, 2, DISABLE, ENABLE); DEFINE_EMC_REG_BIT_ENUM(FBIO_CFG7_CH1_ENABLE, 2, DISABLE, ENABLE);
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0, 16, DISABLE, ENABLE); DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0, 16, DISABLE, ENABLE);
@ -620,3 +631,4 @@ DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_TRAIN_QPOP, 1, D
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_RX_E_DIRECT_ZI, 2, DISABLED, ENABLED); DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_RX_E_DIRECT_ZI, 2, DISABLED, ENABLED);
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR, 3, DISABLED, ENABLED); DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR, 3, DISABLED, ENABLED);
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_DRV_DQS, 4, DISABLED, ENABLED); DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_DRV_DQS, 4, DISABLED, ENABLED);