diff --git a/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp b/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp
index 74bf76ee..d8a5d432 100644
--- a/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp
+++ b/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp
@@ -35,4 +35,7 @@
 #define DEFINE_AHB_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)                                                               REG_DEFINE_NAMED_THREE_BIT_ENUM(AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
 #define DEFINE_AHB_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
 
-DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_COP, 1, ENABLE, DISABLE);
+DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_COP,     1, ENABLE, DISABLE);
+DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_AHBDMA,  5, ENABLE, DISABLE);
+DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB,     6, ENABLE, DISABLE);
+DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB2,   18, ENABLE, DISABLE);
diff --git a/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp b/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp
index 649ed3f0..ae22a0f7 100644
--- a/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp
+++ b/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp
@@ -198,10 +198,15 @@ DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENA
     HANDLER(L, RTC,           0,  4)    \
     HANDLER(L, TMR,           0,  5)    \
     HANDLER(L, GPIO,          0,  8)    \
+    HANDLER(L, USBD,          0, 22)    \
     HANDLER(L, CACHE2,        0, 31)    \
     HANDLER(H, MEM,           1,  0)    \
+    HANDLER(H, AHBDMA,        1,  1)    \
+    HANDLER(H, APBDMA,        1,  2)    \
+    HANDLER(H, USB2,          1, 26)    \
     HANDLER(H, PMC,           1,  6)    \
     HANDLER(H, FUSE,          1,  7)    \
+    HANDLER(H, KFUSE,         1,  8)    \
     HANDLER(H, I2C5,          1, 15)    \
     HANDLER(H, EMC,           1, 25)    \
     HANDLER(U, CSITE,         2,  9)    \
@@ -213,6 +218,7 @@ DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENA
     HANDLER(V, CPUG,          3,  0)    \
     HANDLER(V, MSELECT,       3,  3)    \
     HANDLER(V, SPDIF_DOUBLER, 3, 22)    \
+    HANDLER(V, ACTMON,        3, 23)    \
     HANDLER(V, TZRAM,         3, 30)    \
     HANDLER(V, SE,            3, 31)    \
     HANDLER(W, PCIERX0,       4,  2)    \
@@ -239,10 +245,12 @@ DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENA
 #define CLK_RST_DEFINE_SET_CLR_REG(REGISTER, DEVICE, REGISTER_INDEX, DEVICE_INDEX)                             \
     DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_SET_SET_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
     DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_CLR_CLR_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
+    DEFINE_CLK_RST_REG_BIT_ENUM(CLK_OUT_ENB_##REGISTER##_CLK_ENB_##DEVICE,     DEVICE_INDEX, DISABLE, ENABLE); \
     DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_CLK_ENB_##DEVICE,         DEVICE_INDEX, DISABLE, ENABLE); \
     DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_SET_SET_##DEVICE##_RST,   DEVICE_INDEX, DISABLE, ENABLE); \
     DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_CLR_CLR_##DEVICE##_RST,   DEVICE_INDEX, DISABLE, ENABLE); \
-    DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_##DEVICE##_RST,           DEVICE_INDEX, DISABLE, ENABLE);
+    DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_##DEVICE##_RST,           DEVICE_INDEX, DISABLE, ENABLE); \
+    DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEVICES_##REGISTER##_SWR_##DEVICE##_RST,   DEVICE_INDEX, DISABLE, ENABLE);
 
 CLK_RST_FOREACH_DEVICE(CLK_RST_DEFINE_SET_CLR_REG)